Buffer access for side-channel attack resistance
US11861051B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 2020 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Jan 5, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A cryptographic accelerator (processor) retrieves data blocks for processing from a memory. These data blocks arrive and are stored in an input buffer in the order they were stored in memory (or other known order)—typically sequentially according to memory address (i.e., in-order.) The processor waits until a certain number of data blocks are available in the input buffer and then randomly selects blocks from the input buffer for processing. This randomizes the processing order of the data blocks. The processing order of data blocks may be randomized within sets of data blocks associated with a single read transaction, or across sets of data blocks associated with multiple read transactions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.