Patent · US Active

Selectable monolithic or external scalable die-to-die interconnection system methodology

US11862557B2 · kind B2 · utility

2Cited by
8References
11Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 23, 2021
Grant dateJan 2, 2024
Priority date
Expiry dateDec 22, 2041

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2225/06586
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Multi-die structures and methods of fabrication are described. In an embodiment, a multi-die structure includes a first die, a second die, and die-to-die routing connecting the first die to the second die. The die-to-die interconnection may be monolithically integrated as a chip-level die-to-die routing, or external package-level die-to-die routing.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.