Systems and methods for releveled bump planes for chiplets
US11862604B2 · kind B2 · utility
0Cited by
130References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2021 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Apr 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/381
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.