Inner spacer structure and methods of forming such
US11862709B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2021 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Jun 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.