Unwanted peak reduction in equalizer
US11863170B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2022 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Jul 21, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03878
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An equalizer circuit includes: a main stage circuit including: a main stage differential pair; and a main stage degeneration resistance; a replica stage circuit including: a replica stage differential pair matching the main stage differential pair; and a replica stage degeneration resistance matching the main stage degeneration resistance and disconnected from the replica stage differential pair; equalizer inputs connected to: gate electrodes of the main stage differential pair; and gate electrodes of the replica stage differential pair; and equalizer outputs connected to: a main stage positive output and a main stage negative output connected to drain electrodes of the main stage differential pair; and a replica stage positive output and a replica stage negative output connected to drain electrodes of the replica stage differential pair, the replica stage positive output connected to the main stage negative output and the replica stage negative output connected to the main stage positive output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.