D-type wholly dissimilar high-speed static set-reset flip flop
US11863187B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2022 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Jun 3, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit is provided. The circuit includes a first master stage, a second master stage, a first slave stage, a first slave stage, and a second slave stage. The first master stage includes a data input line. The second master stage includes an inverse data input line. The first slave stage is coupled to an output of the first master stage. The second slave stage is coupled to an output of the second master stage. The first slave stage generates an output signal during a rising edge of a clock cycle. The second slave stage generates an inverted output signal during the rising edge of the clock cycle. The output signal and the inverted output signal are available concurrently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.