Memory device, integrated circuit device and method
US11864393B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2023 |
| Grant date | Jan 2, 2024 |
| Priority date | — |
| Expiry date | Jan 19, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a bit line, a word line, a memory cell, select bit lines, and a controller. The memory cell includes a first transistor, data storage elements, and second transistors corresponding to the data storage elements. The first transistor includes a gate electrically coupled to the word line, a first source/drain, and a second source/drain. Each of the select bit lines is electrically coupled to a gate of a corresponding second transistor. Each data storage element and the corresponding second transistor are electrically coupled in series between the first source/drain of the first transistor and the bit line. The controller turns ON the first transistor and a selected second transistor, and, while the first transistor and the selected second transistor are turned ON, applies different voltages to the bit line to perform corresponding different operations on the data storage element coupled to the selected second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.