Memory devices with cryptographic components
US11868488B2 · kind B2 · utility
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4References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 28, 2022 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Nov 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller. The memory device can have an array of memory cells, a second error correction code component coupled to the array and configured to correct data from the array, and a cryptographic component coupled to receive the corrected data from the second error correction code component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.