System and method for optimizing emulation throughput by selective application of a clock pattern
US11868694B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2020 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Apr 18, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is disclosed that includes a memory, and a processor configured to perform operations stored in the memory. The processor performs the operations to analyze each of a first set of sequential elements of a plurality of sequential elements to determine an edge of a clock signal pattern of a clock associated with each of the first set of sequential elements causing an output change at corresponding one or more sequential elements of the first set of sequential elements. The processor further performs the operations to discard one or more cycles of the clock signal pattern of the clock from emulation that do not include the edge of the clock signal pattern that causes at least one sequential element of the first set of sequential elements to change the output and emulate remaining cycles of the clock signal pattern of the clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.