Scheduling tasks using work fullness counter
US11868807B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2021 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Dec 16, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of activating scheduling instructions within a parallel processing unit includes checking if an ALU targeted by a decoded instruction is full by checking a value of an ALU work fullness counter stored in the instruction controller and associated with the targeted ALU. If the targeted ALU is not full, the decoded instruction is sent to the targeted ALU for execution and the ALU work fullness counter associated with the targeted ALU is updated. If, however, the targeted ALU is full, a scheduler is triggered to de-activate the scheduled task by changing the scheduled task from the active state to a non-active state. When an ALU changes from being full to not being full, the scheduler is triggered to re-activate an oldest scheduled task waiting for the ALU by removing the oldest scheduled task from the non-active state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.