Selectable fuse sets, and related methods, devices, and systems
US11869620B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2022 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Jan 10, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory devices are disclosed. A device may include a number of memory banks and a number of latch sets, wherein each latch set is associated with a memory bank. The device may also include a fuse array including a number of fuses. The device may further include circuitry configured to read data from a first set of fuses of the number of fuses and broadcast data from the first set of fuses to a first latch set of the number of latch sets. Further, in response to a repair result associated with the first set of fuses being a first state, the circuitry may be configured to read a second set of fuses and broadcast the second set of fuses to the first latch set. Methods of operating a memory device, microelectronic devices, semiconductor devices, and electronic systems are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.