IC having a metal ring thereon for stress reduction
US11869820B2 · kind B2 · utility
0Cited by
2References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2022 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Jul 1, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.