Semiconductor package through hole with lever arms and insulating layers with different coefficient of thermal expansion
US11869828B2 · kind B2 · utility
0Cited by
2References
17Claims
0Family size
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Key dates
| Filing date | Jun 10, 2021 |
| Grant date | Jan 9, 2024 |
| Priority date | — |
| Expiry date | Oct 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/809
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first die. The first die includes a semiconductor substrate. The semiconductor substrate has a first surface, a second surface opposite to the first surface, and a through hole between the first surface and the second surface and having an inner wall. The inner wall has a first lever arm. A length of the first lever arm is less than a thickness of the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.