Enhanced write performance utilizing program interleave
US11875061B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2022 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Apr 28, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a memory sub-system including a single-level cell (SLC) cache, a first multiple level cell (XLC) storage including a first XLC block, and a second XLC storage including a second XLC block. Data is indirectly written to the first XLC storage via the SLC cache in a first XLC write mode, and data is directly written to the second XLC storage in a second XLC write mode. The system further includes a processing device to perform operations including receiving data from a host system, in response to receiving the data, initiating a write operation to write the data to the first XLC storage and the second XLC storage, and causing subsets of the data to be alternatively written to the first XLC block in the first XLC write mode and to the second XLC block in the second XLC write mode using page level interleave.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.