Method for latency detection on a hardware simulation accelerator
US11875095B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 1, 2020 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Mar 23, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for performing automated detection of transaction latency for a processor design model running an application in a hardware simulation accelerator. The method includes loading the processor design model into the hardware simulation accelerator, loading the application into the processor design model running within the hardware simulation accelerator, simulating the processor design model running the application within the hardware simulation accelerator, and for each individual transaction of the application: establishing a first checkpoint at a start of an execution of the individual transaction by creating a breakpoint and resetting a counter, establishing a second checkpoint at a completion of the transaction by creating another breakpoint and obtaining latency information for the second checkpoint. The latencies of the individual transaction from the start to the completion are measured based on the latency information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.