Real-time arbitration of shared resources in a multi-master communication and control system
US11875183B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2019 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | May 29, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/503
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A spinlock circuit connected to one or more first processors through one or more broadside interfaces. The spinlock circuit is configured to receive a plurality of requests for use of a computing resource from one or more first processors, and reply to each of the plurality of requests within a single clock cycle of the one or more first processors. The spinlock circuit can reply to each of the plurality of requests within a single clock cycle of the one or more first processors by alternately assigning the computing resource to a requesting processor from among the one or more first processors or indicating to the requesting processor from among the one or more first processors that the computing resource is not available.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.