Buffer memory adapted to implment calculations having operands as data
US11875848B2 · kind B2 · utility
0Cited by
8References
13Claims
0Family size
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Key dates
| Filing date | Jan 20, 2022 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Jan 20, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2245
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present description concerns a memory device (200) including a non-volatile memory circuit (101); a buffer memory circuit (203) comprising a volatile memory circuit (221); an input-output circuit (105); a first data link (104) coupling the non-volatile memory circuit (101) to the buffer memory circuit (203); a second data link (106) coupling the buffer memory circuit (203) to the input-output circuit (105); and a control circuit (225), wherein the buffer memory circuit (203) is adapted to implementing calculations having as operands data stored in the volatile memory circuit (221).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.