System-on-wafer structure and fabrication method
US11876071B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2023 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Jun 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/81
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system-on-wafer structure and a fabrication method. The structure includes a wafer substrate, an integrated chiplet, a system configuration board and a thermal module. The wafer substrate and the integrated chiplet are bonded through a wafer micro bump array and a chiplet micro bump array. The wafer substrate and the system configuration board are bonded through a copper pillar array on wafer substrate topside and a pad on system configuration board backside. A molding layer is provided between the wafer substrate and the system configuration board, and is configured to mold the wafer substrate, the integrated chiplet and the copper pillar array. Integrated chiplet are electrically connected to each other through a re-distributed layer in wafer substrate. The integrated chiplet is electrically connected to the system configuration board through the re-distributed layer and the copper pillar array. The thermal module is attached to the backside of the wafer substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.