Process for collectively fabricating a plurality of semiconductor structures
US11876073B2 · kind B2 · utility
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3References
18Claims
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Inventor
Key dates
| Filing date | Oct 24, 2019 |
| Grant date | Jan 16, 2024 |
| Priority date | — |
| Expiry date | Apr 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/94
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for collectively fabricating a plurality of semiconductor structures comprises providing a substrate including a carrier having a main face, a dielectric layer on the main face of the carrier and a plurality of crystalline semiconductor growth islands on the dielectric layer. At least one crystalline semiconductor active layer is formed on the growth islands. After the step of forming the active layer, trenches are formed in the active layer and in the growth islands in order to define the plurality of semiconductor structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.