ESD protection circuit

US11876090B2 · kind B2 · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• David Michael Rogers · Sunnyvale, US
• Eric N. Mann · Issaquah, US
• Eric Lee Swindlehurst · Marysville, US
• Toru Miyamae · Kasugai, JP
• Timothy Williams · Bellevue, US
• Ryuta Nagai · Kasugai, JP
• Sungkwon Lee · Eden Prairie, US
• Ravindra M. Kapre · San Jose, US
• Mimi Qian · Campbell, US
• Yan Yi · Mountain View, US
• Dung Si Ho · Sunnyvale, US
• Boo Chin-Hua · Kampung Bukit Kechil, MY

Key dates

• Filing date: Nov 17, 2022
• Grant date: Jan 16, 2024
• Expiry date: Nov 17, 2042

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/911

Abstract

An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.