Error rate interrupts in hardware for high-speed signaling interconnect
US11880265B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2021 |
| Grant date | Jan 23, 2024 |
| Priority date | — |
| Expiry date | Dec 21, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A receiver device includes detection logic, an error counter, and an interrupt logic. The detection logic is to receive a first set of data frames and detect one or more frame errors in the first set of data frames. The error counter is to store a number of the one or more frame errors detected in the first set of data frames. The interrupt logic can be coupled to the error counter. The interrupt logic is to specify a period and compare the number of the one or more frame errors with a threshold number of frame errors during the period, where the interrupt logic is to indicate an interrupt responsive to the number of the one or more frame errors detected within the period satisfying the threshold number of frame errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.