Semiconductor device including a memory array performing a multiplication and accumulation (MAC) operation using capacitors
US11881243B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 11, 2021 |
| Grant date | Jan 23, 2024 |
| Priority date | — |
| Expiry date | May 17, 2042 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a memory cell array including a plurality of memory cells coupled between a multiplicity of word lines and one or more bit lines; and an operation circuit configured to perform a multiplication and accumulation (MAC) operation with one or more first multi-bit data provided from the one or more bit lines and one or more second multi-bit data, wherein a plurality of memory cells coupled to a bit line store a plurality of bits included in a corresponding one of the one or more first multi-bit data, and wherein the memory cell array sequentially provides the plurality of bits included in the corresponding first multi-bit data to the operation circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.