Semiconductor memory device and memory system including memory cell arrays and column selection transistors arranged to improve size efficiency
US11881283B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 1, 2021 |
| Grant date | Jan 23, 2024 |
| Priority date | — |
| Expiry date | Jan 29, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes first and second memory cell arrays spaced apart from each other in a first direction, a plurality of column selection transistors in a second direction which intersects the first direction, between the first and second memory cell arrays, at least two of the column selection transistors include respective portions of a central gate pattern, which intersects a central line extending in the first direction at a center of the first memory cell array and has a closed loop shape, and first and second local input/output lines configured to provide electric potential through the first memory cell array to a local sense amplifier based on operations of the column selection transistors. The first and second local input/output lines are electrically connected to the central gate pattern, and the center line is spaced apart from and does not intersect the first and second local input/output lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.