SOI active transfer board for three-dimensional packaging and preparation method thereof
US11881442B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2020 |
| Grant date | Jan 23, 2024 |
| Priority date | — |
| Expiry date | Jun 26, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/854
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is an SOI active interposer for three-dimensional packaging and a fabrication method thereof. An SOI substrate is used as the substrate, and a CMOS inverter is formed on the top silicon of the SOI by using standard integrated circuit manufacturing processes, so that short channel effect and latch-up effect can be suppressed. A via hole structure is etched on the SOI substrate between the PMOS and NMOS transistors of the CMOS inverter, which on the one hand can be used as a conductive channel between the chips in a vertical direction, and on the other hand, can be used as an electrical isolation layer between the PMOS and NMOS transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.