Through silicon buried power rail implemented backside power distribution network semiconductor architecture and method of manufacturing the same
US11881455B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2021 |
| Grant date | Jan 23, 2024 |
| Priority date | — |
| Expiry date | Jan 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0149
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor architecture including a wafer, a first semiconductor device provided on a first surface of the wafer, the first semiconductor device being configured to route signals, a second semiconductor device provided on a second surface of the wafer opposite to the first surface of the wafer, the second semiconductor device being configured to supply power, and a buried power rail (BPR) included inside of the wafer and extending from the first surface of the wafer to the second surface of the wafer, the BPR being configured to deliver the power from the second semiconductor device to the first semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.