Dummy poly layout for high density devices
US11881477B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2020 |
| Grant date | Jan 23, 2024 |
| Priority date | — |
| Expiry date | Dec 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/962
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array of poly lines on an active device area of an integrated chip is extended to form a dummy device structure on an adjacent isolation region. The resulting dummy device structure is an array of poly lines having the same line width, line spacing, and pitch as the array of poly lines on the active device area. The poly lines of the dummy device structure are on grid with the poly lines on the active device area. Because the dummy device structure is formed of poly lines that are on grid with the poly lines on the active device area, the dummy device structure may be much closer to the active device area than would otherwise be possible. The resulting proximity of the dummy device structure to the active device area improves anti-dishing performance and reduces empty space on the integrated chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.