Reduction of low frequency noise in a discrete spread spectrum timebase
US11881767B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 13, 2019 |
| Grant date | Jan 23, 2024 |
| Priority date | — |
| Expiry date | Apr 6, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/1586
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An integrated circuit. The integrated circuit comprises a timebase generator and a switch mode direct current-to-direct current (DC-to-DC) voltage converter coupled to the timebase generator. The timebase generator comprises a first linear feedback shift register (LFSR), a signal generator having an input coupled to an output of the first LFSR; and a digital divider comprising a second LFSR and a programmable digital divider, wherein a clock input of the programmable digital divider is coupled to an output of the signal generator, wherein an output of the programmable digital divider is coupled to a clock input of the first LFSR and is coupled to a clock input of the second LFSR, and wherein an output of the second LFSR is coupled to a program input of the programmable digital divider.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.