Calibration scheme for filling lookup table in an ADC
US11881867B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2021 |
| Grant date | Jan 23, 2024 |
| Priority date | — |
| Expiry date | Sep 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/365
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.