Memory devices
US11887653B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2022 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Jun 18, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a memory device including a row decoder generating word line (WL) control signals based on a row address from an external device, a first sub-array including memory cells connected to word lines, a first sub-word line driver (SWD) providing a selection voltage or a non-selection voltage to odd-numbered word lines of the word lines based on odd-numbered WL control signals corresponding to the odd-numbered word lines, and a second SWD providing the selection voltage or the non-selection voltage to even-numbered word lines of the word lines based on even-numbered WL control signals corresponding to the even-numbered word lines. The first SWD applies the non-selection voltage to non-selection word lines of the even-numbered word lines, in response to the even-numbered WL control signals, and the second SWD applies the non-selection voltage to non-selection word lines of the odd-numbered word lines, in response to the odd-numbered WL control signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.