Through silicon via structure for three-dimensional integrated circuit packaging and manufacturing method thereof
US11887912B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 2, 2020 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Jun 20, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/14181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure belongs to the technical field of integrated circuit packaging, and specifically relates to a through silicon via structure for three-dimensional integrated circuit packaging and a manufacturing method thereof. The method of the present disclosure includes the following steps: lifting off a silicon wafer by implanting hydrogen ions into the silicon wafer to obtain a substrate for making a through silicon via; performing double-sided plasma etching on the substrate to form a through silicon via penetrating the substrate; depositing an insulating medium, a copper diffusion barrier layer, and a seed layer; and removing parts of the copper diffusion barrier layer and the seed layer by photolithography and etching processes, leaving only parts of the copper diffusion barrier layer and the seed layer on a sidewall of the through silicon via; forming a sacrificial layer on the upper and lower surfaces of the resulting structure, completely filling in the through silicon via with conductive metal material, and then removing the sacrificial layer, upper and lower surfaces of the conductive metal material respectively protruding from upper and lower surfaces of the ins…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.