Wafer-level heterogeneous dies integration structure and method
US11887964B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 11, 2023 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Apr 11, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/182
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer-level heterogeneous dies integration structure and method are provided. The integration structure includes a wafer substrate, a silicon interposer, heterogeneous dies, and a configuration substrate. A standard integration module is defined by the heterogeneous dies connected to the silicon interposer. The standard integration module is connected to an upper surface of the wafer substrate, and the configuration substrate is connected to a lower surface of the wafer substrate. The wafer substrate is connected to the configuration substrate via Through Silicon Vias on lower surface of the wafer substrate. And the upper surface of the wafer substrate is provided with Re-distributed Layers and a standardized micro bump array to form standard integration zone connected to the standard integration module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.