Semiconductor wafer with devices having different top layer thicknesses
US11887987B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2022 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | May 27, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit includes a base silicon layer, a base oxide layer, a first top silicon layer, a second top silicon layer, a first semiconductor device, and a second semiconductor device. The base oxide layer is formed over the base silicon layer. The first top silicon layer is formed over a first region of the base oxide layer and has a first thickness. The second top silicon layer is formed over a second region of the base oxide layer and has a second thickness less than the first thickness. The first semiconductor device is formed over the first top silicon layer and the second semiconductor device is formed over the second top silicon layer. The ability to fabricate a top silicon layers with differing thicknesses can provide a single substrate having devices with different characteristics, such as having both fully depleted and partially depleted devices on a single substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.