Semiconductor device having a liner layer and method of fabricating the same
US11888028B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2022 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Jul 12, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0167
Abstract
A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.