Master, slave, master-slave-communication system, on-chip interconnect system, method for operating a master, method for operating a slave, method for operating a master-slave communication system and method for operating an on-chip interconnect system
US11888618B2 · kind B2 · utility
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3References
21Claims
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Key dates
| Filing date | Mar 15, 2022 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Mar 15, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/40019
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A master is provided which is connected to at least one slave via an interface, wherein the at least one master is designed, in a transmission mode to transfer a valid combination of output data and associated error detection data via the interface, and wherein the at least one master is furthermore designed, in a non-transmission mode, to output an invalid combination of output data and associated error detection data in case of an erroneous output request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.