Integrated assemblies and methods of forming integrated assemblies
US11889691B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2021 |
| Grant date | Jan 30, 2024 |
| Priority date | — |
| Expiry date | Oct 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.