Semiconductor device and test method of semiconductor device
US11892503B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2022 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Aug 29, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1438
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes first and second chips in a package. A first pad is on the first chip and electrically connected to a node between a power supply pad and a ground pad on the first chip. Second and third pads are on the second chip. An internal wiring connects the first pad to the second pad within the package. A power circuit on the semiconductor chip configured to supply a current to the second pad. A switch is on the second chip between the second pad and the power supply circuit to connect or disconnect the second pad from the power circuit. A control circuit is on the second chip and configured to output a first signal for the switch in response to a test signal supplied to the third pad and a second signal to the power circuit to cause the power circuit to output current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.