Patent · US Active

System and method for flash and RAM allocation for reduced power consumption in a processor

US11893249B2 · kind B2 · utility

0Cited by

0References

19Claims

0Family size

Assignee

Ceremorphic, Inc. · US

Inventors

Subba Reddy Kallam · Sunnyvale, US
Partha Sarathy Murali · San Jose, US
Venkata Siva Prasad Pulagam · Secunderabad, IN
Anusha Biyyani · Hyderabad, IN
Venkatesh Vinjamuri · Theni, IN
Shahabuddin Mohammed · Hyderabad, IN
Rahul Kumar Gurram · Secunderabad, IN
Akhil Dharamprakash Soni · Kalpi, IN

Key dates

Filing date	Mar 9, 2022
Grant date	Feb 6, 2024
Priority date	—
Expiry date	Mar 9, 2042

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

The present invention is an controller for dynamically allocating RAM between powersave code copied from ROM and transient RAM memory used for storing packets. When the utilization of the transient RAM memory is low, code segments are copied from ROM and executed from RAM using a RAM pointer table which is updated after the code segments are copied over from ROM, and when the utilization of the transient RAM memory is high, code segments are deallocated from RAM and the pointer table is updated to point to the corresponding location in flash ROM.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.