Time-tagging read levels of multiple wordlines for open block data retention
US11894080B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2022 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Aug 3, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: acquire a first set of read levels on a wordline of a first block of pages of memory cells; acquire a second set of read levels on a first wordline of a second block of pages of a second set of memory cells in response to determining that the fail bit count of the page after a read operation is above the threshold amount; and acquire a third set of read levels on a second wordline of the second block in response to determining that the fail bit count of the page after the second read operation is above the threshold amount.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.