Wafer level package
US11894338B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2022 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Feb 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.