Patent · US Active

Power enhanced stacked chip scale package solution with integrated die attach film

US11894344B2 · kind B2 · utility

0Cited by

2References

19Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Zhijun Xu · Shanghai, CN
Bin Liu · Fishers, US
Yong She · Shanghai, CN
Zhicheng Ding · Shanghai, CN

Key dates

Filing date	Apr 6, 2022
Grant date	Feb 6, 2024
Priority date	—
Expiry date	Apr 6, 2042

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/1434
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.