Set of integrated standard cells
US11894382B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Dec 7, 2021 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Dec 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/907
Abstract
An integrated circuit includes at least a first standard cell framed by two second standard cells. The three cells are disposed adjacent to each other, and each standard cell includes at least one NMOS transistor and at least one least one PMOS transistor located in and on a silicon-on-insulator substrate. The at least one PMOS transistor of the first standard cell has a channel including silicon and germanium. The at least one PMOS transistor of each second standard cell has a silicon channel and a threshold voltage different in absolute value from the threshold voltage of said at least one PMOS transistor of the first cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.