Olivier Weber
18Patents
3h-index
35Co-inventors
56Inventor score
Filing activity: Feb 28, 2008 → Jul 5, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8006410B2 | Shoe, particularly sport or leisure shoe | Human Necessities | 50 | Active |
| US9653538B2 | Method of localized modification of the stresses in a substrate of the SOI type, in particular FD SOI type, and corresponding device | Electricity | 4 | Active |
| US9929146B2 | Method of forming MOS and bipolar transistors | Electricity | 4 | Active |
| US9190334B2 | SOI integrated circuit comprising adjacent cells of different types | Electricity | 3 | Active |
| US11653582B2 | Chip containing an onboard non-volatile memory comprising a phase-change material | Physics | 2 | Active |
| US9099354B2 | Transistors with various levels of threshold voltages and absence of distortions between nMOS and pMOS | Electricity | 1 | Active |
| US10381344B2 | Method of forming MOS and bipolar transistors | Electricity | 0 | Active |
| US10381478B2 | Method of localized modification of the stresses in a substrate of the SOI type, in particular FD SOI type, and corresponding device | Electricity | 0 | Active |
| US11818901B2 | Integrated circuit including bipolar transistors | Electricity | 0 | Active |
| US11723220B2 | Strained transistors and phase change memory | Electricity | 0 | Active |
| US12144187B2 | Strained transistors and phase change memory | Electricity | 0 | Active |
| US12328858B2 | Silicon-on-insulator semiconductor device with a static random access memory circuit | Electricity | 0 | Active |
| US9876032B2 | Method of manufacturing a device with MOS transistors | Electricity | 0 | Active |
| US12232435B2 | Chip containing an onboard non-volatile memory comprising a phase-change material | Physics | 0 | Active |
| US10482957B2 | Resistive RAM memory cell | Physics | 0 | Active |
| US11152430B2 | Integrated circuit including bipolar transistors | Electricity | 0 | Active |
| US10332808B2 | Device comprising multiple gate structures and method of simultaneously manufacturing different transistors | Electricity | 0 | Active |
| US11894382B2 | Set of integrated standard cells | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.