Ultra-high-speed PAM-N CMOS inverter serial link
US11894959B2 · kind B2 · utility
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41References
21Claims
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Key dates
| Filing date | Jul 25, 2022 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Jul 25, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/04
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and apparatus described herein make a multi-level PAM signal (PAM-N signal) at a transmitter using CMOS-based components. By forming the PAM-N signal at the transmitter, receivers do not have to recombine and/or realign multiple signals and only employs a single transmission line channel (or two transmission line channels in differential implementations) to convey the data stream to the receiver from the transmitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.