Vertical non-volatile memory devices having a multi-stack structure with enhanced photolithographic alignment characteristics
US11895827B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2021 |
| Grant date | Feb 6, 2024 |
| Priority date | — |
| Expiry date | Jan 11, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A vertical-type nonvolatile memory device has a multi-stack structure with reduced susceptibility to mis-alignment of a vertical channel layer. This nonvolatile memory device includes: (i) a main chip area including a cell area and an extension area arranged to have a stepped structure, with the cell area and the extension area formed in a multi-stack structure, and (ii) an outer chip area, which surrounds the main chip area and includes a step key therein. The main chip area includes a first layer on a substrate and a second layer on the first layer. A lower vertical channel layer is arranged in the first layer. The step key includes an alignment vertical channel layer, and a top surface of the alignment vertical channel layer is lower than a top surface of the lower vertical channel layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.