Frame alignment recovery for a high-speed signaling interconnect
US11899609B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2021 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Jan 2, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system includes a first device and a second device coupled to a link having one or more lanes. The first device is to transmit two or more frames to synchronize the one or more data lanes, where each frame comprises a quantity of bits. The second device is to receive a first set of bits from each data lane corresponding to the quantity of bits in each frame of the two or more frames. The second device is to determine that the first set of bits received from a data lane of the one or more data lanes does not correspond to a frame boundary of the two or more frames. The second device is further to synchronize each data lane of the one or more data lanes with respect to the frame boundary, responsive to determining that the first set of bits does not correspond to the frame boundary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.