Semiconductor storage device having reduced threshold distribution interference
US11901011B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2021 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Feb 25, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor storage device includes a first word line, a second word line provided in the same layer with the first word line and configured to be controlled independently from the first word line, a plurality of memory pillars between the first word line and the second word line, each of the plurality of memory pillars including a first memory cell facing to the first word line and a second memory cell facing to the second word line, the plurality of memory pillars being arranged in a first direction and a second direction intersecting to the first direction and a control circuit. The control circuit is configured to perform a write operation to the second memory cell included in the plurality of memory pillars after performing a write operation to the first memory cell included in each of the plurality of memory pillars.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.