Sense amplifier structure for non-volatile memory with neighbor bit line local data bus data transfer
US11901018B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2021 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Jun 28, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A local data bus of a sense amplifier associated with one bit line is used to perform logical operations for a sensing operation performed by another sense amplifier associated with a different bit line. Each sense amplifier circuit includes a sensing node that is pre-charged, then discharged through a selected memory cell and a local data bus with a number of data latches connected. Target program data can be stored in the latches and combined in logical combinations with the sensed value of the memory cell to determine whether it has verified. By including a transfer circuit between the local data buses of a pair of sense amplifiers, the logical operations of a first sense amplifier can be performed using the local data bus of the paired sense amplifier, freeing the first sense amplifier's sense node to be concurrently pre-charged for a subsequent sensing operation, thereby improving performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.