Use of data latches for compression of soft bit data in non-volatile memories
US11901019B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2022 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Feb 8, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.