Fin field-effect transistor device and method of forming the same
US11901183B2 · kind B2 · utility
1Cited by
14References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 9, 2021 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Sep 5, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.