Semiconductor devices including lower electrodes including inner protective layer and outer protective layer
US11901291B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2021 |
| Grant date | Feb 13, 2024 |
| Priority date | — |
| Expiry date | Sep 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad, the lower electrode including an outer protective layer, a conductive layer between opposing sidewalls of the outer protective layer, and an inner protective layer between opposing sidewalls of the conductive layer, a first supporter pattern on a side surface of the lower electrode, the first supporter pattern including a supporter hole, a dielectric layer on a surface of each of the lower electrode and the first supporter pattern, and an upper electrode on the dielectric layer. The outer protective layer includes titanium oxide, the conductive layer includes titanium nitride, and the inner protective layer includes titanium silicon nitride. In a horizontal cross-sectional view, the outer protective layer has an arc shape that extends between the dielectric layer and the conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.